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XC1700E and XC1700L Series Configuration PROMs
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DS027 (v3.1) July 5, 2000
Product Specification
Features
* One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices Simple interface to the FPGA; requires only one user I/O pin Cascadable for storing longer or multiple bitstreams Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions XC17128E/EL, XC17256E/EL, XC1701 and XC1700L series support fast configuration Low-power CMOS Floating Gate process XC1700E series are available in 5V and 3.3V versions XC1700L series are available in 3.3V only Available in compact plastic packages: 8-pin SOIC, 8-pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC, 44-pin PLCC or 44-pin VQFP. Programming support by leading programmer manufacturers. Design support using the Xilinx Alliance and Foundation series software packages. Guaranteed 20 year life data retention
Description
The XC1700 family of configuration PROMs provides an easy-to-use, cost-effective method for storing large Xilinx FPGA configuration bitstreams. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal. Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family. For device programming, either the Xilinx Alliance or Foundation series development system compiles the FPGA design file into a standard Hex format, which is then transferred to most commercial PROM programmers.
* * * * * * * *
* * *
VCC
VPP
GND
RESET/ OE or OE/ RESET
CE
CEO
CLK
Address Counter
TC
EPROM Cell Matrix
Output
OE DATA
DS027_01_021500
Figure 1: Simplified Block Diagram (does not show programming circuit)
(c) 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS027 (v3.1) July 5, 2000 Product Specification
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XC1700E and XC1700L Series Configuration PROMs
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Pin Description
DATA
Data output is in a high-impedance state when either CE or OE are inactive. During programming, the DATA pin is I/O. Note that OE can be programmed to be either active High or active Low.
VPP
Programming voltage. No overshoot above the specified max voltage is permitted on this pin. For normal read operation, this pin must be connected to VCC. Failure to do so may lead to unpredictable, temperature-dependent operation and severe problems in circuit debugging. Do not leave VPP floating!
CLK
Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active.
VCC and GND
Positive supply and ground pins.
PROM Pinouts RESET/OE
When High, this input holds the address counter reset and puts the DATA output in a high-impedance state. The polarity of this input pin is programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE, although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at "0", and puts the DATA output in a high-impedance state. The polarity of this input is programmable. The default is active High RESET, but the preferred option is active Low RESET, because it can be driven by the FPGAs INIT pin. The polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the Xilinx HW-130 Programmer. Third-party programmers have different methods to invert this pin. 8-pin PDIP SOIC 20-pin VOIC SOIC 1 2 3 4 5 6 7 8 1 3 8 10 11 13 18 20 20-pin PLCC 2 4 6 8 10 14 17 20 44-pin VQFP 40 43 13 15 18, 41 21 35 38 44-pin PLCC 2 5 19 21 24, 3 27 41 44
Pin Name DATA CLK RESET/OE (OE/RESET) CE GND CEO VPP VCC
CE
When High, this pin disables the internal address counter, puts the DATA output in a high-impedance state, and forces the device into low-ICC standby mode.
Capacity
Devices XC1704L XC1702L XC1701/L XC17512L XC1736E XC1765E/EL XC17128E/EL XC17256E/EL Configuration Bits 4,194,304 2,097,152 1,048,576 524,288 36,288 65,536 131,072 262,144
CEO
Chip Enable output, to be connected to the CE input of the next PROM in the daisy chain. This output is Low when the CE and OE inputs are both active AND the internal address counter has been incremented beyond its Terminal Count (TC) value. In other words: when the PROM has been read, CEO will follow CE as long as OE is active. When OE goes inactive, CEO stays High until the PROM is reset. Note that OE can be programmed to be either active High or active Low.
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DS027 (v3.1) July 5, 2000 Product Specification
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XC1700E and XC1700L Series Configuration PROMs Configuration Bits 106,288 165,488 237,744 559,232 781,248 1,041,128 1,335,872 1,751,840 2,546,080 3,608,000 4,715,648 6,127,776 630,048 863,840 1,442,106 1,875,648 2,693,440 3,340,400 3,961,632 6,519,648 6,587,520 8,308,992 10,159,648 12,922,336 16,283,712
Xilinx FPGAs and Compatible PROMs
Device XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4002XL XC4005XL XC4010XL XC4013XL/XLA XC4020XL/XLA XC4028XL/XLA XC4028EX XC4036EX/XL/XLA XC4036EX XC4044XL/XLA XC4052XL/XLA XC4062XL/XLA XC4085XL/XLA XC40110XV XC40150XV XC40200XV XC40250XV XC5202 XC5204 Configuration Bits 53,984 95,008 119,840 147,552 178,144 247,968 329,312 422,176 61,100 151,960 283,424 393,632 521,880 668,184 668,184 832,528 832,528 1,014,928 1,215,368 1,433,864 1,924,992 2,686,136 3,373,448 4,551,056 5,433,888 42,416 70,704 Device PROM XC17128E(1) XC17128E XC17128E XC17256E XC17256E XC17256E XC1701 XC1701 XC17128EL(1) XC17256EL XC17512L XC17512L XC17512L XC1701L XC1701 XC1701L XC1701 XC1701L XC1702L XC1702L XC1702L XC1704L XC1704L XC1704L + XC17512L XC1704L+ XC1702L XC1765E XC17128E XCV1000 XCV50E XCV100E XCV200E XCV300E XCV400E XCV405E XCV600E XCV812E XCV1000E XCV1600E XCV2000E XCV2600E XCV3200E XC5206 XC5210 XC5215 XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800
PROM XC17128E XC17256E XC17256E XC1701L XC1701L XC1701L XC1702L XC1702L XC1704L XC1704L XC1704L + XC1701L XC1704L + XC1702L XC1701L XC1701L XC1702L XC1702L XC1704L XC1704L XC1704L 2 of XC1704L 2 of XC1704L 2 of XC1704L 3 of XC1704L 4 of XC1704L 4 of XC1704L
Notes: 1. The suggested PROM is determined by compatibility with the higher configuration frequency of the Xilinx FPGA CCLK. Designers using the default slow configuration frequency (CCLK) can use the XC1765E or XC1765EL for the noted FPGA devices.
DS027 (v3.1) July 5, 2000 Product Specification
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XC1700E and XC1700L Series Configuration PROMs
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Controlling PROMs
Connecting the FPGA device with the PROM. * * * * The DATA output(s) of the of the PROM(s) drives the DIN input of the lead FPGA device. The Master FPGA CCLK output drives the CLK input(s) of the PROM(s). The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). The RESET/OE input of all PROMs is best driven by the INIT output of the lead FPGA device. This connection assures that the PROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a VCC glitch. Other methods--such as driving RESET/OE from LDC or system reset--assume the PROM internal power-on-reset is always in step with the FPGA's internal power-on-reset. This may not be a safe assumption. The PROM CE input can be driven from either the LDC or DONE pins. Using LDC avoids potential contention on the DIN pin. The CE input of the lead (or only) PROM is driven by the DONE output of the lead FPGA device, provided that DONE is not permanently grounded. Otherwise, LDC can be used to drive CE, but must then be unconditionally High during user operation. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 10 mA maximum.
read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK. If the user-programmable, dual-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal operation. The Xilinx FPGA families take care of this automatically with an on-chip default pull-up resistor.
Programming the FPGA With Counters Unchanged Upon Completion
When multiple FPGA-configurations for a single FPGA are stored in a PROM, the OE pin should be tied Low. Upon power-up, the internal address counters are reset and configuration begins with the first program stored in memory. Since the OE pin is held Low, the address counters are left unchanged after configuration is complete. Therefore, to reprogram the FPGA with another program, the DONE line is pulled Low and configuration begins at the last value of the address counters. This method fails if a user applies RESET during the FPGA configuration process. The FPGA aborts the configuration and then restarts a new configuration, as intended, but the PROM does not reset its address counter, since it never saw a High level on its OE input. The new configuration, therefore, reads the remaining data in the PROM and interprets it as preamble, length count etc. Since the FPGA is the master, it issues the necessary number of CCLK pulses, up to 16 million (224) and DONE goes High. However, the FPGA configuration will be completely wrong, with potential contentions inside the FPGA and on its output pins. This method must, therefore, never be used when there is any chance of external reset during configuration.
*
*
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block (CLB) and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the configuration program from an external memory. The Xilinx PROMs have been designed for compatibility with the Master Serial mode. Upon power-up or reconfiguration, an FPGA enters the Master Serial mode whenever all three of the FPGA mode-select pins are Low (M0=0, M1=0, M2=0). Data is read from the PROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated during configuration. Master Serial Mode provides a simple configuration interface. Only a serial data line and two control lines are required to configure an FPGA. Data from the PROM is
Cascading Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cascaded PROMs provide additional memory. After the last bit from the first PROM is read, the next clock signal to the PROM asserts its CEO output Low and disables its DATA line. The second PROM recognizes the Low level on its CE input and enables its DATA output. See Figure 2. After configuration is complete, the address counters of all cascaded PROMs are reset if the FPGA RESET pin goes Low, assuming the PROM reset polarity option has been inverted. To reprogram the FPGA with another program, the DONE line goes Low and configuration begins where the address counters had stopped. In this case, avoid contention between DATA and the configured I/O use of DIN.
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DS027 (v3.1) July 5, 2000 Product Specification
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XC1700E and XC1700L Series Configuration PROMs
VCC
DOUT
OPTIONAL Daisy-chained FPGAs with Different configurations OPTIONAL Slave FPGAs with Identical Configurations VCC
FPGA
MODES*
3.3V 4.7K
VCC DIN RESET RESET CCLK DONE INIT
* For mode pin connections, refer to the appropriate FPGA data sheet.
VPP DATA
DATA CLK CE OE/RESET
PROM
CEO
CLK CE
Cascaded Serial Memory
OE/RESET
(Low Resets the Address Pointer) CCLK (Output)
DIN
DOUT (Output)
DS027_02_060100
Figure 2: Master Serial Mode. The one-time-programmable PROM supports automatic loading of configuration programs. Multiple devices can be cascaded to support additional FPGAs. An early DONE inhibits the PROM data output one CCLK cycle before the FPGA I/Os become active.
DS027 (v3.1) July 5, 2000 Product Specification
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XC1700E and XC1700L Series Configuration PROMs
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Standby Mode
The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high impedance state regardless of the state of the OE input.
Programming
The devices can be programmed on programmers supplied by Xilinx or qualified third-party vendors. The user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. The wrong choice can permanently damage the device.
Table 1: Truth Table for XC1700 Control Inputs Control Inputs RESET Inactive Active Inactive Active CE Low Low High High Internal Address If address < TC(1): increment If address > TC(2): don't change Held reset Not changing Held reset DATA Active High-Z High-Z High-Z High-Z Outputs CEO High Low High High High ICC Active Reduced Active Standby Standby
Notes: 1. The XC1700 RESET input has programmable polarity 2. TC = Terminal Count = highest address value. TC + 1 = address 0.
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DS027 (v3.1) July 5, 2000 Product Specification
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XC1700E and XC1700L Series Configuration PROMs
XC1701, XC1736E, XC1765E, XC17128E and XC17256E Absolute Maximum Ratings
Symbol VCC VPP VIN VTS TSTG TSOL Description Supply voltage relative to GND Supply voltage relative to GND Input voltage relative to GND Voltage applied to High-Z output Storage temperature (ambient) Maximum soldering temperature (10s @ 1/16 in.) Conditions -0.5 to +7.0 -0.5 to +12.5 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 Units V V V V
C C
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Operating Conditions (5V Supply)
Symbol VCC(1) Description Supply voltage relative to GND (TA = 0C to +70C) Supply voltage relative to GND (TA = -40C to +85C)
Notes: 1. During normal read operation VPP MUST be connect to VCC.
Min Commercial Industrial 4.750 4.50
Max 5.25 5.50
Units V V
DC Characteristics Over Operating Condition
Symbol VIH VIL VOH VOL VOH VOL ICCA ICCS ICCS IL CIN COUT High-level input voltage Low-level input voltage High-level output voltage (IOH = -4 mA) Low-level output voltage (IOL = +4 mA) High-level output voltage (IOH = -4 mA) Low-level output voltage (IOL = +4 mA) Supply current, active mode (at maximum frequency) Supply current, standby mode Supply current, standby mode (XC1701) Input or output leakage current Input capacitance (VIN = GND, f = 1.0 MHz) Output capacitance (VIN = GND, f = 1.0 MHz) Industrial Commercial Description Min 2 0 3.86 3.76 -10 Max VCC 0.8 0.32 0.37 10 50 100 10 10 10 Units V V V V V V mA
mA mA mA
pF pF
DS027 (v3.1) July 5, 2000 Product Specification
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XC1700E and XC1700L Series Configuration PROMs
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XC1704L, XC1702L, XC1701L, XC17512L, XC1765EL, XC17128EL and XC17256EL Absolute Maximum Ratings
Symbol VCC VPP VIN VTS TSTG TSOL Description Supply voltage relative to GND Supply voltage relative to GND Input voltage relative to GND Voltage applied to High-Z output Storage temperature (ambient) Maximum soldering temperature (10s @ 1/16 in.) Conditions -0.5 to +7.0 -0.5 to +12.5 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 Units V V V V
C C
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Operating Conditions (3V Supply)
Symbol VCC(1) Description Supply voltage relative to GND (TA = 0C to +70C) Supply voltage relative to GND (TA = -40C to +85C)
Notes: 1. During normal read operation VPP MUST be connect to VCC.
Min Commercial Industrial 3.0 3.0
Max 3.6 3.6
Units V V
DC Characteristics Over Operating Condition
Symbol VIH VIL VOH VOL ICCA ICCA ICCS ICCS IL CIN COUT High-level input voltage Low-level input voltage High-level output voltage (IOH = -3 mA) Low-level output voltage (IOL = +3 mA) Supply current, active mode (at maximum frequency) (XC1700L) Supply current, active mode (at maximum frequency) (XC1765EL, XC17128EL, XC17256EL) Supply current, standby mode (XC1701L, XC17512L, XC17256L, X1765EL, XC17128EL) Supply current, standby mode (XC1702L, XC1704L) Input or output leakage current Input capacitance (VIN = GND, f = 1.0 MHz) Output capacitance (VIN = GND, f = 1.0 MHz) Description Min 2 0 2.4 -10 Max VCC 0.8 0.4 10 5 50 350 10 10 10 Units V V V V mA mA
mA mA mA
pF pF
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DS027 (v3.1) July 5, 2000 Product Specification
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XC1700E and XC1700L Series Configuration PROMs
AC Characteristics Over Operating Condition
CE
TSCE TSCE THCE
RESET/OE
TLC THC THOE TCYC
CLK
TOE TCE TCAC TOH TDF
DATA
TOH
DS027_03_021500
XC1701, XC17128E, XC17256E Symbol TOE TCE TCAC TDF TOH TCYC TLC THC TSCE THCE THOE Description OE to data delay CE to data delay CLK to data delay CE or OE to data float delay(2,3) Data hold from CE, OE, or CLK(3) Clock periods CLK Low time(3) CLK High time(3) CE setup time to CLK (to guarantee proper counting) CE hold time to CLK (to guarantee proper counting) OE hold time (guarantees counters are reset) Min 0 67 20 20 20 0 20 Max 25 45 45 50 -
XC17128EL, XC17256EL, XC1704L, XC1702L, XC1701L, XC17512L Min 0 67 25 25 25 0 25 Max 30 45 45 50 -
XC1736E, XC1765E Min 0 100 50 50 25 0 100 Max 45 60 80 50 -
XC1765EL Min 0 400 100 100 40 0 100 Max 40 60 200 50 Units ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. AC test load = 50 pF 2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
DS027 (v3.1) July 5, 2000 Product Specification
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XC1700E and XC1700L Series Configuration PROMs
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AC Characteristics Over Operating Condition When Cascading
RESET/OE
CE
CLK TCDF DATA Last Bit TOCK CEO TOCE TOCE
DS027_04_021500
First Bit TOOE
Symbol TCDF TOCK TOCE TOOE
Description CLK to data float delay(2,3) CLK to CEO delay(3) CE to CEO delay(3) RESET/OE to CEO delay(3)
Min -
Max 50 30 35 30
Units ns ns ns ns
Notes: 1. AC test load = 50 pF 2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
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DS027 (v3.1) July 5, 2000 Product Specification
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XC1700E and XC1700L Series Configuration PROMs
Ordering Information
XC1701L PC20 C
Device Number XC1736E XC1765E XC1765EL XC17128E XC17128EL XC17256E XC17256EL XC17512L XC1701 XC1701L XC1704L XC1702L Package Type PD8 SO8 VO8 SO20 PC20 VQ44 PC44 = = = = = = = 8-pin Plastic DIP 8-pin Plastic Small-Outline Package 8-pin Plastic Small-Outline Thin Package 20-pin Plastic Small-Outline Package 20-pin Plastic Leaded Chip Carrier 44-pin Plastic Quad Flat Package 44-pin Plastic Chip Carrier Operating Range/Processing C = Commercial (TA = 0 to +70C) I = Industrial (TA = -40 to +85C)
Valid Ordering Combinations
XC1736EPD8C XC1736ESO8C XC1736EVO8C XC1736EPC20C XC1736EPD8I XC1736ESO8I XC1736EVO8I XC1736EPC20I XC1765EPD8C XC1765ESO8C XC1765EVO8C XC1765EPC20C XC1765EPD8I XC1765ESO8I XC1765EVO8I XC1765EPC20I XC1765ELPD8C XC1765ELSO8C XC1765ELVO8C XC1765ELPC20C XC1765ELPD8I XC1765ELSO8I XC1765ELVO8I XC1765ELPC20I XC17128ELPD8C XC17128ELVO8C XC17128ELPD8I XC17128ELVO8I XC17128ELPC20I XC17256ELPD8C XC17256ELVO8C XC17256ELPD8I XC17256ELVO8I XC17256ELPC20I XC1701LPD8C XC1701LPC20C XC1701LSO20C XC1701LPD8I XC1701LPC20I XC1701LSO20I XC17128EPD8C XC17128EVO8C XC17128EPC20C XC17128EPD8I XC17128EVO8I XC17128EPC20I XC17256EPD8C XC17256EVO8C XC17256EPC20C XC17256EPD8I XC17256EVO8I XC17256EPC20I XC1701PD8C XC1701PC20C XC1701SO20C XC1701PD8I XC1701PC20I XC1701SO20I XC1702LVQ44C XC1702LPC44C XC1704LVQ44C XC1704LPC44C XC1702LVQ44I XC1702LPC44I XC1704LVQ44I XC1704LPC44I XC17512LPD8C XC17512LPC20C XC17512LSO20C XC17512LPD8I XC17512LPC20I XC17512LSO20I
XC17128ELPC20C XC17256ELPC20C
DS027 (v3.1) July 5, 2000 Product Specification
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XC1700E and XC1700L Series Configuration PROMs
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Marking Information
Due to the small size of the commercial serial PROM packages, the complete ordering part number cannot be marked on the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows:
1701L J C
Device Number 1736E 1765E 1765X(1) 17128E 17128X(1) 17256E 17256X(1) 1704L 1702L 1701 1701L 17512L Package Type P S(2) V S(3) J VQ44 PC44 = = = = = = = 8-pin Plastic DIP 8-pin Plastic Small-Outline Package 8-pin Plastic Small-Outline Thin Package 20-pin Plastic Small-Outline Package 20-pin Plastic Leaded Chip Carrier 44-pin Plastic Quad Flat Package 44-pin Plastic Chip Carrier Operating Range/Processing C = Commercial (TA = 0 to +70C) I = Industrial (TA = -40 to +85C)
Notes: 1. When marking the device number on the EL parts, an X is used in place of an EL. 2. For XC1700E/EL only. 3. For XC1700L only.
Revision History
The following table shows the revision history for this document. Date 7/14/98 9/8/98 Version 1.1 2.0 Revision Major revisions to include the XC1704L, XC1702L, and the XQ1701L devices, packages and operating conditions. Also revised the timing specifications on page 9. Revised the marking information for the VQ44. Updated "DC Characteristics Over Operating Condition" on page 7 and page 8. Added references to the XC4000XLA and XC4000XV families in "Xilinx FPGAs and Compatible PROMs" on page 3 and Figure 2 on page 5. Added Virtex FPGAs to "Xilinx FPGAs and Compatible PROMs" on page 3. Added the PC44 package for the XC1702L and XC1704L products. Changed Military ICCS. Changed ICCS standby on XC1702/XC1704 from 50 mA to 300 mA. Combined data sheets XC1700E and XC1700L. Added DS027, removed Military Specs. Added Virtex-E and EM references. Added 4.7K resistor to Figure 2, updated format.
12/18/98 1/27/99 7/8/99 3/30/00 07/05/00
2.1 2.2 2.3 3.0 3.1
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